1. Field of the Invention
The present invention relates to electrical interconnect structures for interconnecting a plurality of devices, such as semiconductor devices. In particular, to methods of making interconnect structures having air gaps in the dielectric material between the interconnect lines of the interconnect structure.
2. Discussion of Related Art
The semiconductor industry is continually pursuing smaller and smaller geometries of the structures used in semiconductor devices. As the device geometries become smaller, more devices are fabricated into the same area of semiconductor substrate. Therefore, the number of interconnect lines in the same area of substrate must also increase, thus requiring that the spacing between the interconnect lines to also decrease in size. This results in increased intra-line capacitance and cross-talk between the closely spaced interconnect lines.
In order to reduce intra-line capacitance and cross-talk between interconnect lines, it is desirable to use a material between the interconnect lines that has a low dielectric constant (low-k). Since air has a low dielectric constant, it is desirable to have air gaps in the dielectric material between the interconnect lines to lower the capacitance between the interconnect lines. One of the issues related to making air gap interconnects is the removal of a sacrificial inter-metal-dielectric (IMD), which is later substituted by a non-conformal chemical vapor deposition (CVD) dielectric to form the air gaps. The removal of the sacrificial IMD can be difficult, having problems with the removal of residues, which can have a detrimental effect on the intra-line capacitance of the interconnect structure. Use of harsher removal methods may lead to damage to the interconnect metals, such as copper. Often additional, and/or longer, more complex processing steps may be employed to remove any remaining polymer and/or post-etch residues remaining after the removal of the sacrificial IMD. Such post-etch treatments may be performed for up to 5 minutes, in addition to time for loading and unloading the substrate, wafer processing start-up and shut-down times for each wafer, and increased down time due to increased usage of the equipment, thus reducing wafer throughput for the method of making an interconnect structure, particularly when making air gaps for the interconnect structure.